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74VHC4046 - CMOS Phase Lock Loop

Download the 74VHC4046 datasheet PDF. This datasheet also covers the 74VHC variant, as both devices belong to the same cmos phase lock loop family and are provided as variant models within a single manufacturer datasheet.

General Description

The VHC4046 is a low power phase lock loop utilizing advanced silicon-gate CMOS technology to obtain high frequency operation both in the phase comparator and VCO sections.

This device contains a low power linear voltage controlled oscillator (VCO), a source follower, and three phase comparators.

Key Features

  • s Low dynamic power consumption: s Maximum VCO operating frequency: (VCC = 4.5V) s Fast comparator response time (VCC = 4.5V) Comparator I: Comparator II: Comparator III: 25 ns 30 ns 25 ns (VCC = 4.5V) 12 MHz s VCO has high linearity and high temperature stability s Pin and function compatible with the 74HC4046 Ordering Code: Order Number 74VHC4046M 74VHC4046MTC 74VHC4046N Package Number M16A MTC16 N16E Package.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74VHC-4046.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com 74VHC4046 CMOS Phase Lock Loop April 1994 Revised October 2003 74VHC4046 CMOS Phase Lock Loop General Description The VHC4046 is a low power phase lock loop utilizing advanced silicon-gate CMOS technology to obtain high frequency operation both in the phase comparator and VCO sections. This device contains a low power linear voltage controlled oscillator (VCO), a source follower, and three phase comparators. The three phase comparators have a common signal input and a common comparator input. The signal input has a self biasing amplifier allowing signals to be either capacitively coupled to the phase comparators with a small signal or directly coupled with standard input logic levels.