96LS02 Datasheet PDF

Fairchild Semiconductor 96LS02

This allows the designer to employ either leading-edge or trailing-edge triggering which is independent of input transition times When input conditions for triggering are met a new cycle starts and the external capacitor is allowed to rapidly discharge and then charge again The retriggerable feature permits output pulse widths to be extended In fact a continuous true output can be maintained by having an input cycle time which is shorter than the output cycle time The output pulse may then be terminated at any time by applying a low logic level to the RESET pin Retriggering may be inhibited...