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CD4022BC - Divide-by-8 Counter/Divider

Download the CD4022BC datasheet PDF. This datasheet also covers the CD4022BCM variant, as both devices belong to the same divide-by-8 counter/divider family and are provided as variant models within a single manufacturer datasheet.

General Description

The CD4017BC is a 5-stage divide-by-10 Johnson counter with 10 decoded outputs and a carry out bit.

The CD4022BC is a 4-stage divide-by-8 Johnson counter with 8 decoded outputs and a carry-out bit.

These counters are cleared to their zero count by a logical “1” on their reset line.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CD4022BCM_FairchildSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CD4022BC Divide-by-8 Counter/Divider National Semiconductor
CD4022B CMOS COUNTER/DIVIDERS RCA
CD4022B CMOS COUNTER/DIVIDERS Texas Instruments
CD4022BM Divide-by-8 Counter/Divider National Semiconductor
CD4022BMS CMOS Counter/Dividers Intersil Corporation

Other Datasheets by Fairchild (now onsemi)

Part Number Description
CD4027BC Dual J-K Master/Slave Flip-Flop
CD4027BCM Dual J-K Master/Slave Flip-Flop
CD4027BCN Dual J-K Master/Slave Flip-Flop
CD4007C Dual Complementary Pair Plus Inverter
CD4007CM Dual Complementary Pair Plus Inverter

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CD4017BC • CD4022BC Decade Counter/Divider with 10 Decoded Outputs • Divide-by-8 Counter/Divider with 8 Decoded Outputs October 1987 Revised January 1999 CD4017BC • CD4022BC Decade Counter/Divider with 10 Decoded Outputs • Divide-by-8 Counter/Divider with 8 Decoded Outputs General Description The CD4017BC is a 5-stage divide-by-10 Johnson counter with 10 decoded outputs and a carry out bit. The CD4022BC is a 4-stage divide-by-8 Johnson counter with 8 decoded outputs and a carry-out bit. These counters are cleared to their zero count by a logical “1” on their reset line. These counters are advanced on the positive edge of the clock signal when the clock enable signal is in the logical “0” state.