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DM7474N - Dual Positive-Edge-Triggered D-Type Flip-Flop

Download the DM7474N datasheet PDF. This datasheet also covers the DM7474 variant, as both devices belong to the same dual positive-edge-triggered d-type flip-flop family and are provided as variant models within a single manufacturer datasheet.

General Description

This device contains two independent positive-edge-triggered D-type flip-flops with complementary outputs.

The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DM7474_FairchildSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
DM7474 Dual Positive-Edge-Triggered D Flip-Flops National Semiconductor
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Other Datasheets by Fairchild (now onsemi)

Part Number Description
DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flop
DM7474M Dual Positive-Edge-Triggered D-Type Flip-Flop
DM7473 Dual Master-Slave J-K Flip-Flop
DM7476 Dual Master-Slave J-K Flip-Flop
DM7400 Quad 2-Input NAND Gates

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs September 1986 Revised July 2001 DM7474 Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs General Description This device contains two independent positive-edge-triggered D-type flip-flops with complementary outputs. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated.