DM7476 Datasheet | Fairchild Semiconductor

DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and plementary Outputs September 1986 Revised February 2000 DM7476 Dual Master-Slave J-K Flip-Flops with Clear, Preset, and plementary Outputs General Description This device contains two independent positive pulse triggered J-K flip-flops with plementary outputs. The J and K data is processed by the flip-flop after a plete clock pulse. While the clock is LOW the slave is isolated from the master. On the positive transition of the clock, the data from the J and K inputs is transferred to the master. While the clock is HIGH the J and K inputs are disabled. On the negative transition of the clock, the data from the...