GENERAL DESCRIPTION
Information at input J or K is transferred to the Q output on the positive going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive going pulse. Asynchronous preset and clear inputs will set or clear Q output respectively upon the application of low level signal. The J-K design allows operation as a D flip-flop by tying the J and K inputs together. FEATURES
s Switching specifications at 50 pF s Switching specifications guaranteed over full temperature and VCC range s Advanced oxide-isolated, ion-implanted Schottky TTL process s Functionally and pin for pin compatible with Schottky and LS TTL counterpart s Improved AC performance over LS109 at approximately half the power Ordering Code: Order Number DM74ALS109AM DM74ALS109AN Package Number M16A N16E Package DESCRIPTION
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel.
Fairchild Semiconductor
