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DM74ALS165 - 8-Bit Parallel In/Serial Out Shift Register

General Description

The DM74ALS165 is an 8-bit serial register that, when clocked, shifts the data toward serial output, QH.

Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the SH/LD input.

Key Features

  • a clock inhibit function and a complemented serial output, QH. Clocking is accomplished by a LOW-to-HIGH transition of the CLK input while SH/LD is held HIGH and CLK INH is held LOW. The functions of the CLK and CLK INH (clock inhibit) inputs are interchangeable. Since a LOW CLK input and a LOW-to-HIGH transition of CLK INH will also accomplish clocking, CLK INH should be changed to the high level only while the CLK input is HIGH. Parallel loading is inhibited when SH/LD is held HIGH. The parall.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DM74ALS165 8-Bit Parallel In/Serial Out Shift Register January 1986 Revised February 2000 DM74ALS165 8-Bit Parallel In/Serial Out Shift Register General Description The DM74ALS165 is an 8-bit serial register that, when clocked, shifts the data toward serial output, QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the SH/LD input. The DM74ALS165 also features a clock inhibit function and a complemented serial output, QH. Clocking is accomplished by a LOW-to-HIGH transition of the CLK input while SH/LD is held HIGH and CLK INH is held LOW. The functions of the CLK and CLK INH (clock inhibit) inputs are interchangeable.