DM74AS161 Datasheet | Fairchild Semiconductor

Description These synchronous presettable counters feature an internal carry look ahead for application in high speed counting designs. The DM74AS161 and DM74AS163 are 4-bit binary counters. The DM74AS161 clear asynchronously, while the DM74AS163 clear synchronously. The carry output is decoded to prevent spikes during normal counting mode of operation. Synchronous operation is provided by having all flip-flops clocked simultaneously so that outputs change coincident with each other when so instructed by count enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. These counters are fully programmable, that is, the outputs may each be preset to either level. As presetting is synchronous, setting up a low level at the LOAD input disables the counter and causes the outputs to agree with set up data after the next clock pulse regardless of the levels of enable input. LOW-to-HIGH transitions at the LOAD input are perfectly acceptable regardless of the logic levels on the clock or enable inputs. The DM74AS161 clear function is asynchronous. A low level at the clear input sets all four of the flip-flop outputs LOW regardless of the levels of clock, load or enable inputs. This counter is provided with a clear on power-up feature . The DM74AS163 clear function is synchronous; and a low level at the clear input sets all four of the flip-flop outputs LOW after the next clock pulse, regardless of the levels of enable inputs. This synchronous clear allows the count length to be modified easily, as decoding the maximum count desired can be acplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to all LOW outputs. LOW-to-HIGH transitions at the clear input of the DM74AS163 is also...