GENERAL DESCRIPTION
These synchronous presettable counters feature an internal carry look ahead for application in high speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that outputs change coincident with each other when so instructed by count enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. These counters are fully programmable, that is, the outputs may each be preset to either level. As presetting is synchronous, setting up a low level at the LOAD input disables the counter and causes the outputs to agree with set up data after the next clock pulse regardless of the levels of enable input. LOW-to-HIGH transitions at the LOAD input are perfectly acceptable regardless of the logic levels on the clock or enable inputs.
Fairchild Semiconductor
