GENERAL DESCRIPTION
These dual 4-bit inverting registers feature totem-pole 3STATE outputs designed specifically for driving highlycapacitive or relatively low-impedance loads. The highimpedance state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of On the positive transition of the clock, the Q outputs will be set to the logic states that were set up at the D inputs. A buffered output control input can be used to place the eight outputs in either a normal logic state (HIGH or LOW logic levels) or a high-impedance state. In the high-impedance state the outputs neither load nor drive the bus lines significantly. That is, the old data can be retained or new data can be entered even while the outputs are OFF.
Fairchild Semiconductor
