This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs.
The J and K data is processed by the flip-flop on the falling edge of the clock pulse.
| Part number | DM74KS112AM |
|---|---|
| Manufacturer | Fairchild (onsemi) |
| File Size | 52.01 KB |
| Description | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset/ Clear/ and Complementary Outputs |
| Datasheet |
 DM74KS112AM Datasheet
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| Part Number | Description | Manufacturer |
|---|---|---|
| DM7400 | Quad 2-Input NAND Gates | National Semiconductor |
| DM7401 | Quad 2-Input NAND Gates with Open-Collector Outputs | National Semiconductor |
| DM7402 | Quad 2-Input NOR Gates | National Semiconductor |
| DM7404 | Hex Inverting Gates | National Semiconductor |
| DM7405 | (DM5405 / DM7405) Hex Inverters | National Semiconductor |
| Part Number | Description |
|---|---|
| DM7400 | Quad 2-Input NAND Gates |
| DM7402 | Quad 2-Input NOR Gates |
| DM7403 | Quad 2-Input NAND Gates with Open-Collector Outputs |
| DM7404 | Hex Inverting Gates |
| DM7405 | Hex Inverters |
The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.
