Datasheet Details
| Part number | DM74LS112A |
|---|---|
| Manufacturer | Fairchild (now onsemi) |
| File Size | 52.01 KB |
| Description | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop |
| Datasheet | DM74LS112A_FairchildSemiconductor.pdf |
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Overview: DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and plementary Outputs August 1986 Revised March 2000 DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with.
| Part number | DM74LS112A |
|---|---|
| Manufacturer | Fairchild (now onsemi) |
| File Size | 52.01 KB |
| Description | Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop |
| Datasheet | DM74LS112A_FairchildSemiconductor.pdf |
|
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|
This device contains two independent negative-edge-triggered J-K flip-flops with plementary outputs.
The J and K data is processed by the flip-flop on the falling edge of the clock pulse.
The clock triggering occurs at a voltage level and is not directly related to the transition time of the falling edge of the clock pulse.
| Brand Logo | Part Number | Description | Manufacturer |
|---|---|---|---|
 |
DM74LS112A | NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS | National Semiconductor |
| Part Number | Description |
|---|---|
| DM74LS11 | Triple 3-Input AND Gate |
| DM74LS10 | Triple 3-Input NAND Gate |
| DM74LS109A | Dual Positive-Edge-Triggered J-K Flip-Flop |
| DM74LS123 | Dual Retriggerable One-Shot |
| DM74LS125A | Quad 3-STATE Buffer |
| DM74LS126A | Quad 3-STATE Buffer |
| DM74LS132 | Quad 2-Input NAND Gate |
| DM74LS136 | Quad 2-Input Exclusive-OR Gate |
| DM74LS138 | Decoder/Demultiplexer |
| DM74LS139 | Decoder/Demultiplexer |