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DM74LS139 - Decoder/Demultiplexer

Download the DM74LS139 datasheet PDF. This datasheet also covers the DM74LS138 variant, as both devices belong to the same decoder/demultiplexer family and are provided as variant models within a single manufacturer datasheet.

General Description

These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times.

In high-performance memory systems these decoders can be used to minimize the effects of system decoding.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DM74LS138_FairchildSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
DM74LS139 Decoders/Demultiplexers National Semiconductor
DM74LS132 NAND Gates National Semiconductor
DM74LS138 Decoders/Demultiplexers National Semiconductor
DM74LS10 Triple 3-Input NAND Gates National Semiconductor
DM74LS107A Dual Negative-Edge- Triggered Master-Slave J-K Flip-Flops National Semiconductor

Other Datasheets by Fairchild (now onsemi)

Part Number Description
DM74LS132 Quad 2-Input NAND Gate
DM74LS136 Quad 2-Input Exclusive-OR Gate
DM74LS138 Decoder/Demultiplexer
DM74LS10 Triple 3-Input NAND Gate
DM74LS109A Dual Positive-Edge-Triggered J-K Flip-Flop

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DM74LS138 • DM74LS139 Decoder/Demultiplexer August 1986 Revised March 2000 DM74LS138 • DM74LS139 Decoder/Demultiplexer General Description These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times. In high-performance memory systems these decoders can be used to minimize the effects of system decoding. When used with high-speed memories, the delay times of these decoders are usually less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. The DM74LS138 decodes one-of-eight lines, based upon the conditions at the three binary select inputs and the three enable inputs.