DM74LS164 Datasheet | Fairchild Semiconductor

Description These 8-bit shift registers feature gated serial inputs and an asynchronous clear. A low logic level at either input inhibits entry of the new data, and resets the first flip-flop to the low level at the next clock pulse, thus providing plete control over ining data. A high logic level on either input enables the other input, which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is HIGH or LOW, but only information meeting the setup and hold time requirements will be entered. Clocking occurs on the LOW-to-HIGH level transition of the clock input. All inputs are diode-clamped to minimize transmission-line effects. Features s Gated (enable/disable) serial inputs s Fully buffered clock and serial inputs s Asynchronous clear s Typical clock frequency 36 MHz s Typical power dissipation 80 m W Ordering Code: Order Number DM74LS164M DM74LS164N Package Number M14A N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Inputs Clear L H H H H Clock X L ↑ ↑ ↑ A X X H L X B X X H X L QA L QA0 H L L Outputs QB L QB0 QAn QAn QAn ... ... ... ... ... ... QH L QH0 QGn QGn QGn H = HIGH Level (steady state) L = LOW Level (steady state) X = Don't Care (any input, including transitions) ↑ = Transition from LOW-to-HIGH level QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established. QAn, QGn = The level of QA or QG before the most recent ↑ transition of the clock; indicates a one-bit shift. © 2000 Fairchild Semiconductor Corporation DS006398 .fairchildsemi. Logic Diagram Timing Diagram .fairchildsemi. Absolute Maximum Ratings(Note 1) Supply Voltage Input...