Datasheet4U Logo Datasheet4U.com

DM74LS165 - 8-Bit Parallel In/Serial Output Shift Registers

General Description

This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked.

Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input.

Key Features

  • s Complementary outputs s Direct overriding (data) inputs s Gated clock inputs s Parallel-to-serial data conversion s Typical frequency 35 MHz s Typical power dissipation 105 mW Ordering Code: Order Number DM74LS165M DM74LS165WM DM74LS165N Package Number M16A M16B N16E Package.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
DM74LS161A Synchronous 4-Bit Binary Counters National Semiconductor
DM74LS163A Synchronous 4-Bit Binary Counters National Semiconductor
DM74LS164 8-Bit Serial In/Parallel Out Shift Registers National Semiconductor
DM74LS166 8-Bit Parallel-In/Serial-Out Shift Registers National Semiconductor
DM74LS169A Synchronous 4-Bit Up/Down Binary Counter National Semiconductor

Other Datasheets by Fairchild (now onsemi)

Part Number Description
DM74LS161A Synchronous 4-Bit Binary Counters
DM74LS163A Synchronous 4-Bit Binary Counters
DM74LS164 8-Bit Serial In/Parallel Out Shift Register
DM74LS166 8-Bit Parallel-In/Serial-Out Shift Register
DM74LS169A Synchronous 4-Bit Up/Down Binary Counter

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DM74LS165 8-Bit Parallel In/Serial Output Shift Registers August 1986 Revised March 2000 DM74LS165 8-Bit Parallel In/Serial Output Shift Registers General Description This device is an 8-bit serial shift register which shifts data in the direction of QA toward QH when clocked. Parallel-in access is made available by eight individual direct data inputs, which are enabled by a low level at the shift/load input. These registers also feature gated clock inputs and complementary outputs from the eighth bit. Clocking is accomplished through a 2-input NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs HIGH inhibits clocking, and holding either clock input LOW with the load input HIGH enables the other clock input.