DM74LS365A Datasheet | Fairchild Semiconductor

DM74LS365A Hex 3-STATE Buffer/Bus Driver August 1986 Revised March 2000 Hex 3-STATE Buffer/Bus Driver General Description This device contains six independent gates each of which performs a non-inverting buffer function. The outputs have the 3-STATE feature. When enabled, the outputs exhibit the low impedance characteristics of a standard LS output with additional drive capability to permit the driving of bus lines without external resistors. When disabled, both the output transistors are turned OFF presenting a high-impedance state to the bus line. Thus the output will act neither as a significant load nor as a driver. To minimize the possibility that two outputs will attempt to take a mon bus to opposite logic levels, the disable time is shorter than the enable time of the outputs. Ordering Code: Order Number Package Number Package Description DM74LS365AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS365AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Y=A Input G1 G2 H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level Hi-Z = 3-STATE (Outputs are disabled) Output Y Hi-Z Hi-Z © 2000 Fairchild Semiconductor Corporation DS006427 .fairchildsemi....