DM96L02 Datasheet | Fairchild Semiconductor

Description The DM96L02 is a dual TTL monostable multivibrator with trigger mode selection, reset capability, rapid recovery, internally pensated reference levels and high speed capability. Output pulse duration and accuracy depend on external timing ponents, and are therefore under user control for each application. It is well suited for a broad variety of applications, including pulse delay generators, square wave generators, long delay timers, pulse absence detectors, frequency detectors, clock pulse generators and fixed-frequency dividers. Each input is provided with a clamp diode to limit undershoot and minimize ringing induced by fast fall times acting on system wiring impedances. Features s Retriggerable, 0% to 100% duty cycle s DC level triggering, insensitive to transition times s Leading or trailing-edge triggering s plementary outputs with active pull-ups s Pulse width pensation for ∆VCC and ∆TA s 50 ns to ∞ output pulse width range s Optional retrigger lock-out capability s Resettable, for interrupt operations Ordering Code: Order Number DM96L02N Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Logic Symbol Connection Diagram VCC = Pin 16 GND = Pin 8 Pin Descriptions Pin Names I0 I1 CD Q Q CX RX Description Trigger Input (Active Falling Edge) Trigger Input (Active Rising Edge) Direct Clear Input (Active LOW) Positive Pulse Output plementary Pulse Output External Capacitor Connection External Resistor Connection © 2000 Fairchild Semiconductor Corporation DS010203 .fairchildsemi. Functional Block Diagram Operation Notes 1. TRIGGERING- can be acplished by a positivegoing transition on pin 4 (12) or a negative-going transition on pin 5 (11). Triggering begins as a signal crosses the input VIL:VIH threshold region; this activates an internal latch whose unbalanced cross-coupling causes it to assume a preferred state. As the latch output goes LOW it disables the gates leading to...