FIN1025 Datasheet | Fairchild Semiconductor

FIN1025 3.3V LVDS 2-Bit High Speed Differential Driver June 2002 Revised June 2002 FIN1025 3.3V LVDS 2-Bit High Speed Differential Driver General Description This dual driver is designed for high speed interconnects utilizing Low Voltage Differential Signaling (LVDS) technology. The driver translates LVTTL signal levels to LVDS levels with a typical differential output swing of 350m V which provides low EMI at ultra low power dissipation even at high frequencies. This device is ideal for high speed transfer of clock and data. The FIN1025 can be paired with its panion receiver, the FIN1026, or any other LVDS receiver. Features s Greater than 400Mbs data rate s Flow-through pinout simplifies PCB layout s 3.3V power supply operation s 0.4ns maximum differential pulse skew s 1.7ns maximum propagation delay s Low power dissipation s Power-Off protection s Meets or exceeds the TIA/EIA-644 LVDS standard s 14-Lead TSSOP package saves space Ordering Code: Order Number FIN1025MTC Package Number MTC14 Package Description 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Name DIN1, DIN2, DOUT1+, DOUT2+ DOUT1- , DOUT2- EN EN VCC GND NC Description LVTTL Data Inputs Non-Inverting Driver Outputs Inverting Driver Outputs Driver Enable Pin Inverting Driver Enable Pin Power Supply Ground No Connect Truth Table Inputs EN H H H X L or OPEN H = HIGH Logic Level L = LOW Logic Level X = Don’t Care Z = High Impedance Outputs DIN H L OPEN X X DOUT+ H L L Z Z DOUT- L H H Z Z EN L or OPEN L or OPEN L or OPEN H X © 2002 Fairchild Semiconductor Corporation DS500783 .fairchildsemi....