Datasheet4U Logo Datasheet4U.com

FM24C02U - 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM

General Description

The FM24C02U/03U devices are 2048 bits of CMOS non-volatile electrically erasable memory.

These devices conform to all specifications in the Standard IIC 2-wire protocol.

They are designed to minimize device pin count and simplify PC board layout requirements.

Key Features

  • I Extended operating voltage 2.7V.
  • 5.5V I 400 KHz clock frequency (F) at 2.7V - 5.5V I 200µA active current typical 10µA standby current typical 1µA standby current typical (L) 0.1µA standby current typical (LZ) I IIC compatible interface.
  • Provides bi-directional data transfer protocol I Sixteen byte page write mode.
  • Minimizes total write time per byte I Self timed write cycle Typical write cycle time of 6ms I Hardware Write Protect for upper half (FM24C03U only) I End.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
FM24C02 2-Wire Serial EEPROM Fudan
FM24C02A 2-Wire Serial EEPROM Fudan
FM24C02B 2-Wire Serial EEPROM Fudan
FM24C02C 2-Wire Serial EEPROM Fudan
FM24C04 2-Wire Serial EEPROM Fudan

Other Datasheets by Fairchild (now onsemi)

Part Number Description
FM24C03U 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM
FM24C04U 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM
FM24C05U 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM
FM24C08U 4K-Bit Standard 2-Wire Bus Interface Serial EEPROM
FM24C09U 8K-Bit Standard 2-Wire Bus Interface Serial EEPROM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
FM24C02U/03U – 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM August 2000 FM24C02U/03U – 2K-Bit Standard 2-Wire Bus Interface Serial EEPROM General Description The FM24C02U/03U devices are 2048 bits of CMOS non-volatile electrically erasable memory. These devices conform to all specifications in the Standard IIC 2-wire protocol. They are designed to minimize device pin count and simplify PC board layout requirements. The upper half (upper 1Kbit) of the memory of the FM24C03U can be write protected by connecting the WP pin to VCC. This section of memory then becomes unalterable unless WP is switched to VSS. This communications protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s).