FM25C640U Datasheet | Fairchild Semiconductor

Description The FM25C640U is a 64K bit serial interface CMOS EEPROM (Electrically Erasable Programmable Read-Only Memory). This device fully conforms to the SPI 4-wire protocol which uses Chip Select (/CS), Clock (SCK), Data-in (SI) and Data-out (SO) pins to synchronously control data transfer between the SPI microcontroller and the EEPROM. In addition, the serial interface allows a minimal pin count, packaging designed to simplify PC board layout requirements and offers the designer a variety of low voltage and low power options. This SPI EEPROM family is designed to work with the 68HC11 or any other SPI-patible, high-speed microcontroller and offers both hardware (/WP pin) and software ("block write") data protection. For example, entering a 2-bit code into the STATUS REGISTER prevents programming in a selected block of memory and all programming can be inhibited by connecting the /WP pin to VSS; allowing the user to protect the entire array or a selected section. In addition, SPI devices feature a /HOLD pin, which allows a temporary interruption of the datastream into the EEPROM. Fairchild EEPROMs are designed and tested for applications requiring high endurance, high reliability, and low power consumption for a continuously reliable non-volatile solution for all markets. Functions I SPI MODE 0 interface I 64K bits organized as 8K x 8 I Extended 2.7V to 5.5V operating voltage I 2.1 MHz operation @ 4.5V - 5.5V I Self-timed programming cycle I "Programming plete" indicated by STATUS REGISTER polling I /WP pin and BLOCK WRITE protection Features I Sequential read of entire array I 32 byte "Page write" mode to minimize total write time per byte I /WP pin and BLOCK WRITE protection to prevent inadvertent programming as well as programming ENABLE and DISABLE opcodes. I /HOLD pin to suspend data transfer I Typical 1µA standby current (ISB) for "L" devices and 0.1µA standby current for "LZ" devices. I Endurance: Up to 1,000,000 data changes I Data retention greater...