GENERAL DESCRIPTION
These P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. FEATURES
-3.4A, -30V. RDS(ON) = 0.13Ω @ VGS = -10V. High density cell design for extremely low RDS(ON). High power and current handling capability in a widely used surface mount package. Rugged and reliable. ________________________________________________________________________________ 5 6 4 3 7 8 2 1 ABSOLUTE MAXIMUM RATINGS
Symbol VDSS VGSS ID PD Parameter Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed Maximum Power Dissipation T A= 25°C unless otherwise noted NDS9400A -30 ± 20 (Note 1a) Units V V A ± 3.4 ± 10 (Note 1a) (Note 1b) (Note 1c) 2.5 1.2 1 -55 to 150 W TJ,TSTG Operating and Storage Temperature Range °C THERMAL CHARACTERISTICS RθJA RθJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case (Note 1a) (Note 1) 50 25 °C/W °C/W © 1997 Fairchild Semiconductor Corpo...