GENERAL DESCRIPTION
The NM25C020 is implemented in Fairchild Semiconductor’s floating gate CMOS process that provides superior endurance and data retention. The serial data transmission of this device requires four signal lines to control the device operation: Chip Select (CS), Clock (SCK), Data In (SI), and Serial Data Out (SO). All programming cycles are completely self-timed and do not require an erase before WRITE. BLOCK WRITE protection is provided by programming the STATUS REGISTER with one of four levels of write protection. Additionally, separate WRITE enable and WRITE disable instructions are provided for data protection. Hardware data protection is provided by the WP pin to protect against inadvertent programming. The HOLD pin allows the serial communication to be suspended without resetting the serial sequence. FEATURES
s 2.1 MHz clock rate @ 2.7V to 5.5V s 2048 bits organized as 256 x 8 s Multiple chips on the same 3-wire bus with separate chip select lines s Self-timed pro...