SSN1N45B Datasheet | Fairchild Semiconductor

Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, .. planar, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and mutation mode. These devices are well suited for electronic ballasts based on half bridge configuration. Features - - - - - - 0.5A, 450V, RDS(on) = 4.25Ω @VGS = 10 V Low gate charge ( typical 6.5 n C) Low Crss ( typical 6.5 p F) 100% avalanche tested Improved dv/dt capability Gate-Source Voltage ± 50V guaranteed ! - ◀ ▲ - - G! TO-92 SSN Series ! Absolute Maximum Ratings Symbol VDSS ID IDM VGSS EAS IAR EAR dv/dt PD TC = 25°C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TC = 25°C) Drain Current - Continuous (TC = 100°C) Drain Current - Pulsed (Note 1) SSN1N45B 450 0.5 0.32 4.0 ± 50 (Note 2) (Note 1) (Note 1) (Note 3) Units V A A A V m J A m J V/ns W W W/°C °C °C Gate-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TA = 25°C) Power Dissipation (TL = 25°C) 108 0.5 0.25 5.5 0.9 2.5 0.02 -55 to +150 300 TJ, Tstg TL - Derate above 25°C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds Thermal Characteristics Symbol RθJL RθJA Parameter Thermal Resistance, Junction-to-Lead Thermal Resistance, Junction-to-Ambient (Note 6a) (Note 6b) Typ --- Max 50 140 Units °C/W °C/W ©2002 Fairchild Semiconductor Corporation Rev. A, November...