SSP7N60B Datasheet | Fairchild Semiconductor

Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, planar, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and mutation mode. These devices are well suited for high efficiency switch mode power supplies. Features - - - - - - - 7.0A, 600V, RDS(on) = 1.2Ω @VGS = 10 V Low gate charge ( typical 38 n C) Low Crss ( typical 23 p F) Fast switching 100% avalanche tested Improved dv/dt capability TO-220F package isolation = 4.0k V (Note 6) G G DS TO-220 SSP Series GD S TO-220F SSS Series Absolute Maximum Ratings Symbol VDSS ID IDM VGSS EAS IAR EAR dv/dt PD TJ, TSTG TL TC = 25°C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TC = 25°C) Drain Current - Continuous (TC = 100°C) Drain Current - Pulsed (Note 1) SSP7N60B 600 7.0 4.4 28 ± 30 (Note 2) (Note 1) (Note 1) (Note 3) SSS7N60B 7.0 - 4.4 - 28 - 420 7.0 14.7 5.5 Units V A A A V m J A m J V/ns W W/°C °C °C Gate-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TC = 25°C) - Derate above 25°C Operating and Storage Temperature Range Maximum lead temperature for soldering purposes, 1/8" from case for 5 seconds 147 1.18 -55 to +150 300 48 0.38 - Drain current limited by maximum junction temperature Thermal Characteristics Symbol RθJC RθCS RθJA Parameter Thermal Resistance, Junction-to-Case Max. Thermal Resistance, Case-to-Sink Typ. Thermal Resistance, Junction-to-Ambient Max. SSP7N60B 0.85 0.5 62.5 SSS7N60B 2.6 -62.5 Units °C/W °C/W °C/W ©2002 Fairchild Semiconductor Corporation Rev. B, June 2002 SSP7N60B/SSS7N60B...