SSTVN16857 Datasheet | Fairchild Semiconductor

Description .. The SSTV16857 is a 14-bit register designed for use with 184 and 232 pin PC1600, 2100, and 2700 DDR DIMM applications. The SSTVN16857 is a 14-bit register designed for use with 184 and 232 pin PC3200 DDR DIMM applications. These devices have a differential input clock, SSTL-2 patible data inputs and a LVCMOS patible RESET input. These devices have been designed for pliance with the JEDEC DDR module and register specifications. The devices are fabricated on an advanced submicron CMOS process and are designed to operate at power supplies of less than 3.6V’s. Features s pliant with DDR-I registered module specifications s Operates at 2.5V r 0.2V VDD s SSTL-2 patible input and output structure s Differential SSTL-2 patible clock inputs s Low power mode when device is reset s Industry standard 48 pin TSSOP package Ordering Code: Order Number SSTV16857MTD SSTVN16857MTD (Preliminary) Package Number MTD48 MTD48 Package Description 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Name Q1-Q14 D1-D14 RESET CK CK VREF VDDQ VDD Description SSTL-2 patible Output SSTL-2 patible Inputs Asynchronous LVCMOS Reset Input Positive Master Clock Input Negative Master Clock Input Voltage Reference Pin for SSTL Level Inputs Power Supply Voltage for Output Signals Power Supply Voltage for Inputs Truth Table RESET L H H H H Dn X or Floating L H X X CK X or Floating CK X or Floating Qn L L H Qn Qn n n L H p p L Logic LOW H Logic HIGH X Don’t Care, but not floating unless noted n LOW-to-HIGH Clock Transition p HIGH-to-LOW Clock Transition © 2005 Fairchild Semiconductor Corporation DS500387 .fairchildsemi. SSTV16857 - SSTVN16857 Functional Description The SSTV16857 and SSTVN16587 are 14-bit registers with SSTL-2...