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TMC2072 Datasheet PDF

Fairchild Semiconductor TMC2072

The TMC2072 Genlocking Video Digitizer samples and quantizes standard analog baseband composite NTSC or PAL video into its 8-bit digital equivalent. It extracts horizontal and vertical sync signals, from which an on-chip PLL generates a line-locked pixel clock for the on-chip 8-bit A/D converter and a double-speed register clock to transfer data to a subsequent video processing subsystem. The chip reports each line’s color burst phase and frequency during the next horizontal sync pulse.
Part No. TMC2072
Datasheet TMC2072 Download
Manufacturer
Fairchild Semiconductor
Description Genlocking Video Digitizer
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TMC2072 datasheet page 1 preview

FEATURES

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● Fully integrated acquisition 3-channel video input multiplexer Two-stage (analog and digital) video clamp Automatic gain adjustment Sync detection and separation Pixel and subpixel adjustment of video-to-sync output timing Genlock to any NTSC or PAL format, including PAL-M and PAL-N Pixel clock generation 8-bit video A/D conversion Standard R-bus serial microprocessor interface User-selectable line-locked pixel rates include: – 12.27 MHz NTSC & PAL-M – 13.5 MHz NTSC & all PAL – 14.75 MHz PAL (non-M) TMC2072-1 only – 15.0 MHz PAL (non-M) TMC2072-1 only Direct interface to Fairchild Semiconductor video encoders and decoders Built-in circuitry for crystal oscillator No tuning or external voltage reference required Space-saving 100-lead MQFP package

DESCRIPTION

A second PLL generates a chroma subcarrier locked to the incoming chroma burst. The TMC2072 includes a three-channel video input multiplexer, analog clamp, variable gain amplifier, and digital back porch clamp.
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