GENERAL DESCRIPTION
Data on the A or B bus will be clocked into the registers as the appropriate clock pin goes to a high logic level. OE and direction pins are provided to control the transceiver function. In the transceiver mode, data present at the high impedance port may be stored in either the A or B register or in both. The select controls can multiplex stored and real time (transparent mode) data. The direction control determines which bus will receive data when the enable control OE is active LOW. In the isolation mode (OE HIGH) A data may be stored in the B register and/or B data may be stored in the A register. FEATURES
s Independent registers for A and B buses s Multiplexed real-time and stored data s Guaranteed output skew s Guaranteed MOS (Multiple Output Switching) Specifications s Output switching specified for both 50 pF and 250 pF, and 500 pF loads s Guaranteed simultaneous switching noise level (VOLP/ VOLV) and dynamic threshold performance (VIHD/VILD) s Glitch free p...