74F413 Datasheet | Fairchild Semiconductor

.. 74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O April 1988 Revised August 1999 74F413 64 x 4 First-In First-Out Buffer Memory with Parallel I/O General Description The F413 is an expandable fall-through type high-speed First-In First-Out (FIFO) buffer memory organized as 64 words by four bits. The 4-bit input and output registers record and transmit, respectively, asynchronous data in parallel form. Control pins on the input and output allow for handshaking and expansion. The 4-bit wide, 62-bit deep fall-through stack has self-contained control logic. Features s Separate input and output clocks s Parallel input and output s Expandable without external logic s 15 MHz data rate s Supply current 160 m A max s Available in SOIC, (300 mil only) Ordering Code: Order Number 74F413PC Package Number N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Unit Loading/Fan Out Pin Names D0- D3 O0- O3 IR SI SO OR MR Description Data Inputs Data Outputs Input Ready Shift In Shift Out Output Ready Master Reset U.L. HIGH/LOW 1.0/0.667 50/13.3 1.0/0.667 1.0/0.667 1.0/0.667 1.0/0.667 1.0/0.667 Input IIH/IIL Output IOH/IOL 20 µA/- 0.4 m A - 1 m A/8 m A 20 µA/- 0.4 m A 20 µA/- 0.4 m A 20 µA/- 0.4 m A 20 µA/- 0.4 m A 20 µA/- 0.4 m A © 1999 Fairchild Semiconductor Corporation DS009541 .fairchildsemi. Functional Description Data Input- Data is entered into the FIFO on D0- D3 inputs. To enter data the Input Ready (IR) should be HIGH, indicating that the first location is ready to accept data. Data then present at the four data inputs is entered into the first location when the Shift In (SI) is brought HIGH. An SI HIGH signal causes the IR to go LOW. Data remains at the first location until SI is brought LOW. When SI is brought LOW and the FIFO is not full, IR will go...