74F676 Datasheet | Fairchild Semiconductor

74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register April 1988 Revised August 1999 74F676 16-Bit Serial/Parallel-In, Serial-Out Shift Register General Description The 74F676 contains 16 flip-flops with provision for synchronous parallel or serial entry and serial output. When the Mode (M) input is HIGH, information present on the parallel data (P0- P15) inputs is entered on the falling edge of the Clock Pulse (CP) input signal. When M is LOW, data is shifted out of the most significant bit position while information present on the Serial (SI) input shifts into the least significant bit position. A HIGH signal on the Chip Select (CS) input prevents both parallel and serial operations. Features s 16-bit parallel-to-serial conversion s 16-bit serial-in, serial-out s Chip select control s Slim 24 lead 300 mil package Ordering Code: Order Number 74F676SC 74F676PC 74F676SPC Package Number M24B N24A N24C Package Description 28-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009588 .fairchildsemi. Unit Loading/Fan Out Pin Names P0- P15 CS CP M SI SO Description Parallel Data Inputs Chip Select Input (Active LOW) Clock Pulse Input (Active LOW) Mode Select Input Serial Data Input Serial Output U.L. HIGH/LOW 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 50/33.3 Input IIH/IIL Output IOH/IOL 20 µA/- 0.6 m A 20 µA/- 0.6 m A 20 µA/- 0.6 m A 20 µA/- 0.6 m A 20 µA/- 0.6 m A - 1 m A/20 m A Functional Description The 16-bit shift register operates in one of three modes, as indicated in the Shift Register Operations Table. HOLD- a HIGH signal on the Chip Select (CS) input prevents clocking, and data is stored in the...