Datasheet4U Logo Datasheet4U.com

74F794 - 8-Bit Register

Datasheet Summary

Description

The 74F794 is an 8-bit register with readback capability designed to store data as well as read the register information back onto the data bus.

The I/O bus (D bus) has 3STATE outputs.

Current sinking capability is 64 mA on both the D and Q busses.

Features

  • s 3-STATE outputs on the I/O port s D and Q output sink capability of 64 mA s Functionally and pin equivalent to the 74LS794 Ordering Code: Order Number 74F794SC 74F794PC Package Number M20B N20A Package.

📥 Download Datasheet

Datasheet preview – 74F794

Datasheet Details

Part number 74F794
Manufacturer Fairchild
File Size 49.99 KB
Description 8-Bit Register
Datasheet download datasheet 74F794 Datasheet
Additional preview pages of the 74F794 datasheet.

📁 Similar Datasheet

  • 74F711-1 - Multiplexers (Philips)
  • 74F711A - Multiplexers (Philips)
  • 74F712-1 - Multiplexers (Philips)
  • 74F712A - Multiplexers (Philips)
  • 74F723-1 - Quad 2-to-1 data selector multiplexer (Philips)
  • 74F723A - Quad 2-to-1 data selector multiplexer (Philips)
  • 74F725-1 - Quad 2-to-1 data selector multiplexer (Philips)
  • 74F725A - Quad 2-to-1 data selector multiplexer (Philips)
  • 74F74 - Dual D-type flip-flop (Philips)
  • 74F74 - Dual D-Type Positive Edge-Triggered Flip-Flop (National)
Other Datasheets by Fairchild
  • 74F74 - Dual D-Type Positive Edge-Triggered Flip-Flop
  • 74F779 - 8-Bit Bidirectional Binary Counter
  • 74F181 - 4-Bit Arithmetic Logic
  • 74F182 - Carry Lookahead Generator
  • 74F189 - 64-Bit RAM
  • 74F190 - Up/Down Decade Counter
  • 74F191 - Up/Down Binary Counter
  • 74F192 - Up/Down Decade Counter

Full PDF Text Transcription

Click to expand full text
74F794 8-Bit Register with Readback March 1990 Revised August 1999 74F794 8-Bit Register with Readback General Description The 74F794 is an 8-bit register with readback capability designed to store data as well as read the register information back onto the data bus. The I/O bus (D bus) has 3STATE outputs. Current sinking capability is 64 mA on both the D and Q busses. Data is loaded into the registers on the LOW-to-HIGH transition of the clock (CP). The output enable (OE) is used to enable data on D0–D7. When OE is LOW, the output of the registers is enabled on D0–D7, enabling D as an output bus. When OE is HIGH, D0–D7 are inputs to the registers configuring D as an input bus.
Published: |