74F845 Datasheet | Fairchild Semiconductor

Description The 74F845 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The 74F845 is functionally- and pin-patible with AMD’s Am29845. Features s 3-STATE outputs s Direct replacement for AMD’s Am29845 Ordering Code: Order Number 74F845SC 74F845SPC Package Number M24B N24C Package Description 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC © 1999 Fairchild Semiconductor Corporation DS009601 .fairchildsemi. Unit Loading/Fan Out Pin Names D0- D7 O0- O7 OE1- OE3 LE CLR PRE Description Data Inputs Data Outputs Output Enables Latch Enable Clear Preset U.L. HIGH/LOW 1.0/1.0 150/40 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 Input IIH/IIL Output IOH/IOL 20 µA/- 0.6 m A - 3.0 µA/24 m A 20 µA/- 0.6 m A 20 µA/- 0.6 m A 20 µA/- 0.6 m A 20 µA/- 0.6 m A Functional Description The 74F845 consists of eight D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup times is latched. Data appears on the bus when the output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. Function Table Inputs CLR PRE OE H H H H H H H H L L L H H H H H H H H L H L H L H H H H L L L L L L H H LE X H H L H H L X X X L L D X L H X L H X X X X X X Internal Output Function Q X L H NC L H NC H L H L H O Z Z Z Z L H NC H L H Z Z High Z High Z High Z Latched Transparent Transparent Latched Preset Clear Preset Latched Latched H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High...