74FR900 Datasheet PDF - Fairchild 9-Bit / 3-Port Latchable Datapath Multiplexer Specs

74FR900 - 9-Bit / 3-Port Latchable Datapath Multiplexer

Datasheet Summary

Description

The 74FR900 is a data bus multiplexer routing any of three 9-bit ports to any other one of the three ports.

Readback of data latched from any port onto itself is also possible.

The 74FR900 maintains separate control of all latch-enable, output enable and select inputs for maximum flexibility.

Features

s 9-bit data ports for systems carrying parity bits s Readback capability for system self checks. s Independent control lines for maximum flexibility s Guaranteed multiple output switching and 250 pF load delays s Outputs optimized for dynamic bus drive capability s PINV parity control facilitates system diagnostics s FR25900 resistor option for driving MOS inputs such as DRAM arrays Ordering Code: Order Number 74FR900SSC Package Number MS48A Package.

Datasheet Details

Part number	74FR900
Manufacturer	Fairchild
File Size	46.65 KB
Description	9-Bit / 3-Port Latchable Datapath Multiplexer
Datasheet	74FR900 Datasheet
Additional preview pages of the 74FR900 datasheet.

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Full PDF Text Transcription

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74FR900 9-Bit, 3-Port Latchable Datapath Multiplexer May 1992 Revised August 1999 74FR900 9-Bit, 3-Port Latchable Datapath Multiplexer General Description The 74FR900 is a data bus multiplexer routing any of three 9-bit ports to any other one of the three ports. Readback of data latched from any port onto itself is also possible. The 74FR900 maintains separate control of all latch-enable, output enable and select inputs for maximum flexibility. PINV allows inversion of the data from the C8 to A8 or B8 path. This is useful for control of the parity bit in systems diagnostics. Fairchild’s 74FR25900 includes 25Ω resistors in series with port A and B outputs. Resistors minimize undershoot and ringing which may damage or corrupt sensitive device inputs driven by these ports.

Published: May 28, 2005 |