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MM74HC259 - 8-Bit Addressable Latch/3-to-8 Line Decoder

General Description

The MM74HC259 device utilizes advanced silicon-gate CMOS technology to implement an 8-bit addressable latch, designed for general purpose storage applications in digital systems.

Q8), 3 address inputs (A, B, and C), a common enab

Key Features

  • s Typical propagation delay: 18 ns s Wide supply range: 2.
  • 6V s Low input current: 1 µA maximum s Low quiescent current: 80 µA maximum (74HC Series) Ordering Code: Order Number MM74HC259M MM74HC259SJ MM74HC259MTC MM74HC259N Package Number Package.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder September 1983 Revised February 1999 MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder General Description The MM74HC259 device utilizes advanced silicon-gate CMOS technology to implement an 8-bit addressable latch, designed for general purpose storage applications in digital systems. The MM74HC259 has a single data input (D), 8 latch outputs (Q1–Q8), 3 address inputs (A, B, and C), a common enable input (G), and a common CLEAR input. To operate this device as an addressable latch, data is held on the D input, and the address of the latch into which the data is to be entered is held on the A, B, and C inputs. When ENABLE is taken LOW the data flows through to the addressed output.