Datasheet4U Logo Datasheet4U.com

MM74HC373 - 3-STATE Octal D-Type Latch

General Description

The MM74HC373 high speed octal D-type latches utilize advanced silicon-gate CMOS technology.

They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads.

Key Features

  • s Typical propagation delay: 18 ns s Wide operating voltage range: 2 to 6 volts s Low input current: 1 PA maximum s Low quiescent current: 80 PA maximum (74 Series) s Output drive capability: 15 LS-TTL loads Ordering Code: Order Number Package Number Package.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
MM74HC374 Octal Flip-Flop National Semiconductor
MM74HC374 3-STATE Octal D-Type Flip-Flop ON Semiconductor
MM74HC32 Quad 2-Input OR Gate ON Semiconductor
MM74HC34 Non-Inverter National Semiconductor
MM74HC365 Hex TRI-STATE Buffer Inverting Hex TRI-STATE Buffer Hex TRI-STATE Buffer Inverting Hex TRI-STATE Buffer National

Other Datasheets by Fairchild (now onsemi)

Part Number Description
MM74HC374 3-STATE Octal D-Type Flip-Flop
MM74HC32 Quad 2-Input OR Gate
MM74HC393 Dual 4-Bit Binary Counter
MM74HC00 Quad 2-Input NAND Gate
MM74HC02 Quad 2-Input NOR Gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
MM74HC373 3-STATE Octal D-Type Latch September 1983 Revised May 2005 MM74HC373 3-STATE Octal D-Type Latch General Description The MM74HC373 high speed octal D-type latches utilize advanced silicon-gate CMOS technology. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. Due to the large output drive capability and the 3-STATE feature, these devices are ideally suited for interfacing with bus lines in a bus organized system. When the LATCH ENABLE input is HIGH, the Q outputs will follow the D inputs. When the LATCH ENABLE goes LOW, data at the D inputs will be retained at the outputs until LATCH ENABLE returns HIGH again.