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MM74HCT138 - 3-to-8 Line Decoder

General Description

The MM74HCT138 decoder utilizes advanced silicon-gate CMOS technology, and are well suited to memory address decoding or data routing applications.

Key Features

  • s TTL input compatible s Typical propagation delay: 20 ns s Low quiescent current: 80 µA maximum (74HCT Series) s Low input current: 1 µA maximum s Fanout of 10 LS-TTL loads Ordering Code: Order Number MM74HCT138M MM74HCT138SJ MM74HCT138MTC MM74HCT138N Package Number M16A M16D MTC16 N16E Package.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MM74HCT138 3-to-8 Line Decoder February 1984 Revised February 1999 MM74HCT138 3-to-8 Line Decoder General Description The MM74HCT138 decoder utilizes advanced silicon-gate CMOS technology, and are well suited to memory address decoding or data routing applications. Both circuits feature high noise immunity and low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic. The MM74HCT138 have 3 binary select inputs (A, B, and C). If the device is enabled these inputs determine which one of the eight normally HIGH outputs will go LOW. Two active LOW and one active HIGH enables (G1, G2A and G2B) are provided to ease the cascading decoders.