NDP6020P - P-Channel Logic Level Enhancement Mode Field Effect Transistor

Product Overview

Fairchild

Datasheet Details

Part number	NDP6020P
Manufacturer	Fairchild
File Size	62.16 KB
Description	P-Channel Logic Level Enhancement Mode Field Effect Transistor
Datasheet	NDP6020P Datasheet
Additional preview pages of the NDP6020P datasheet.

Product details

Description

These logic level P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology.

Features

-24 A, -20 V. RDS(ON) = 0.05 Ω @ VGS= -4.5 V. RDS(ON) = 0.07Ω @ VGS= -2.7 V. RDS(ON) = 0.075 Ω @ VGS= -2.5 V. Critical DC electrical parameters specified at elevated temperature. Rugged internal source-drain diode can eliminate the need for an external Zener diode transient suppressor. 175°C maximum junction temperature rating. High density cell design for extremely low RDS(ON). TO-220 and TO-263 (D2PAK) package for both through hole and surface mount.

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Published: May 12, 2005 |