NM24C65 Datasheet | Fairchild Semiconductor

NM24C65 64K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect PRELIMINARY March 1999 NM24C65 64K-Bit Extended 2-Wire Bus Interface Serial EEPROM with Write Protect General Description: The NM24C65 devices are 65,536 bits of CMOS nonvolatile electrically erasable memory. These devices offer the designer different low voltage and low power options, and they conform to all in the Extended IIC 2-wire protocol. Furthermore, they are designed to minimize device pin count and simplify PC board layout requirements. The upper half of the memory can be disabled (Write Protection) by connecting the WP pin to VCC. This section of memory then bees ROM. This munication protocol uses CLOCK (SCL) and DATA I/O (SDA) lines to synchronously clock data between the master (for example a microprocessor) and the slave EEPROM device(s). Fairchild EEPROMs are designed and tested for applications requiring high endurance, high reliability, and low power consumption. Features : s Extended operating voltage 2.7V - 5.5V s 400 KHz clock frequency (F) at 2.7V - 5.5V s 200µA active current typical 10µA standby current typical 1µA standby typical (L) 0.1µA standby typical (LZ) s IIC patible interface - Provides bidirectional data transfer protocol s 32 byte page write mode - Minimizes total write time per byte s Self timed write cycle Typical write cycle time of 6ms s Hardware write protect for upper block s Endurance: 1,000,000 data changes s Data retention greater than 40 years s Packages available: 8-pin SO, 8-pin DIP s Low VCC programming lockout (3.8V - on Standard VCC devices only). Block Diagram VCC WP SDA START STOP LOGIC CONTROL LOGIC SLAVE ADDRESS REGISTER & PARATOR LOAD A2 A1 A0 WORD ADDRESS COUNTER INC E2PROM ARRAY WRITE LOCKOUT START CYCLE H.V. GENERATION TIMING &CONTROL XDEC R/W YDEC CK DIN DATA REGISTER DOUT DS500042-1 © 1999 Fairchild Semiconductor Corporation NM24C65 Rev. C.3 .fairchildsemi. NM24C65 64K-Bit Extended 2-Wire Bus...