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NM24W16 - 2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect

Description

The NM24Wxx devices are 2048/4096/8192/16,384 bits, respectively, of CMOS non-volatile electrically erasable memory.

These devices conform to all specifications in the IIC 2-wire protocol and are designed to minimize device pin count, and simplify PC board layout requirements.

Features

  • s Hardware Write Protect for entire memory s Low Power CMOS 200µA active current typical 10µA standby current typical 1µA standby typical (L) 0.1µA standby typical (LZ) s IIC Compatible interface.
  • Provides bidirectional data transfer protocol s Sixteen byte page write mode.
  • Minimizes total write time per byte s Self timed write cycle.
  • Typical write cycle time of 6ms s Endurance: 1,000,000 data changes s Data retention greater than 40 years s Packages available: 8-pin D.

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Datasheet Details

Part number NM24W16
Manufacturer Fairchild (onsemi)
File Size 104.71 KB
Description 2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect
Datasheet download datasheet NM24W16 Datasheet

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NM24W02 2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect
NM24W04 2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect
NM24W08 2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect
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Full PDF Text Transcription

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NM24Wxx 2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect PRELIMINARY March 1999 NM24Wxx 2K/4K/8K/16K-Bit Standard 2-Wire Bus Interface Serial EEPROM with Full Array Write Protect General Description The NM24Wxx devices are 2048/4096/8192/16,384 bits, respectively, of CMOS non-volatile electrically erasable memory. These devices conform to all specifications in the IIC 2-wire protocol and are designed to minimize device pin count, and simplify PC board layout requirements. The entire ememory can be disabled (Write Protected) by connecting the WP pin to VCC. The memory then becomes unalterable unless WP is switched to VSS.
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