NM27C128 Datasheet | Fairchild Semiconductor

NM27C128 131,072-Bit (16K x 8) High Performance CMOS EPROM July 1998 NM27C128 131,072-Bit (16K x 8) High Performance CMOS EPROM General Description The NM27C128 is a high performance 128K UV Erasable Electrically Programmable Read Only Memory. It is manufactured with Fairchild’s latest CMOS split gate EPROM technology which enables it to operate at speeds as fast as 90 ns access time over the full operating range. The NM27C128 provides microprocessor-based systems extensive storage capacity for large portions of operating system and application software. Its 90 ns access time provides high speed operation with high-performance CPUs. The NM27C128 offers a single chip solution for the code storage requirements of 100% firmware-based equipment. Frequently-used software routines are quickly executed from EPROM storage, greatly enhancing system utility. The NM27C128 is configured in the standard EPROM pinout which provides an easy upgrade path for systems which are currently using standard EPROMs. The NM27C128 is one member of a high density EPROM Family which range in densities up to 4 Mb. Features s High performance CMOS - 90 ns access time s Fast turn-off for microprocessor patibility s JEDEC standard pin configuration - 28-pin PDIP package - 32-pin chip carrier - 28-pin CERDIP package s Drop-in replacement for 27C128 or 27128 s 40% faster programming time with Fairchild’s turbo algorithm Block Diagram VCC GND VPP Data Outputs O0 - O7 OE PGM CE Output Enable, and Chip Enable Logic Output Buffers .. Y Gating Y Decoder A0 - A14 Address Inputs 131,072-Bit Cell Matrix ....... X Decoder DS011329-1 © 1998 Fairchild Semiconductor Corporation .fairchildsemi. NM27C128 131,072-Bit (16K x 8) High Performance CMOS EPROM Connection Diagrams 27C080 27C040 27C020 27C010 27C512 27C256 A19 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 O0 O1 O2...