T24C512A Datasheet PDF | First-Rank Technology

First-Rank Technology T24C512A

The T24C512 provides 524,288 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device’s cascadable feature allows up to eight devices to share a common two-wire bus. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential.

Part No.	T24C512A
Datasheet	T24C512A Download
Manufacturer	First-Rank Technology
Description	EEPROM
Buy	Stock & Price

GENERAL DESCRIPTION

The devices are available in space-saving 8-pin PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead TSSOP. Pin Configuration Pin Descriptions Shenzhen First-Rank Technology Co., Ltd Version: 1.0 Date: 10, Dec, 2013 Page 2 of 16 Tel:86-755-2666 3145 Website: Block Diagram Fax:86-755-83452525 Shenzhen First-Rank Technology Co., Ltd Version: 1.0 Date: 10, Dec, 2013 Page 3 of 16 Tel:86-755-2666 3145 Website: Fax:86-755-83452525 Pin Descriptions SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is opendrain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other T24Cxx devices. When the pins are hardwired,...