56853 Datasheet | Freescale Semiconductor

Description - 120 MIPS at 120MHz - 12K x 16-bit Program SRAM - 4K x 16-bit Data SRAM - 1K x 16-bit Boot ROM - Access up to 2M words of program memory or 8M of data memory - Chip Select Logic for glue-less interface to ROM and SRAM - Six (6) independent channels of DMA - Enhanced Synchronous Serial Interfaces (ESSI) - Two (2) Serial munication Interfaces (SCI) - Serial Port Interface (SPI) - 8-bit Parallel Host Interface - General Purpose 16-bit Quad Timer - JTAG/Enhanced On-Chip Emulation (On CE™) for unobtrusive, real-time debugging - puter Operating Properly (COP)/Watchdog Timer - Time-of-Day (TOD) - 128 LQFP package - Up to 41 GPIO VDDIO 6 11 VDD 6 VSSIO 10 VSS VDDA 6 VSSA JTAG/ Enhanced On CE Program Controller and Hardware Looping Unit Address Generation Unit 16-Bit 56800E Core Data ALU 16 x 16 + 36 → 36-Bit MAC Three 16-bit Input Registers Four 36-bit Accumulators Bit Manipulation Unit PAB PDB CDBR CDBW Memory Program Memory 12,288 x 16 SRAM Boot ROM 1024 x 16 ROM Data Memory 4,096 x 16 SRAM XDB2 XAB1 XAB2 PAB PDB CDBR CDBW IPBus Bridge (IPBB) IPWDB Decoding Peripherals A0-20 [20:0] D0-D15 [15:0] RD Enable WR Enable CS0-CS3[3:0] or GPIOA0-A3[3:0] Bus Control External Address Bus Switch External Data Bus Switch External Bus Interface Unit ESSI0 or GPIOC IPRDB IPAB DMA Requests Core CLK POR System Bus...