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56F802 - 16-bit Digital Signal Controllers

General Description

Up to 30 MIPS operation at 60MHz core frequency Up to 40 MIPS operation at 80MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation uni

Key Features

  • 1.1.1 Processing Core.
  • Efficient 16-bit 56800 family controller engine with dual Harvard architecture.
  • As many as 40 Million Instructions Per Second (MIPS) at 80 MHz core frequency.
  • Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC).
  • Two 36-bit accumulators including extension bits.
  • 16-bit bidirectional barrel shifter.
  • Parallel instruction set with unique processor addressing modes.
  • Hardware DO and REP loops.
  • Thr.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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56F802 Data Sheet Preliminary Technical Data 56F800 16-bit Digital Signal Controllers DSP56F802 Rev. 9 01/2007 freescale.