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56F805 - 16-bit Digital Signal Controllers

General Description

Added revision history.

Up to 40 MIPS at 80MHz core frequency DSP and MCU functionality in a unifi

Key Features

  • 1.1.1 Processing Core.
  • Efficient 16-bit 56800 family processor engine with dual Harvard architecture.
  • As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency.
  • Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC).
  • Two 36-bit accumulators, including extension bits.
  • 16-bit bidirectional barrel shifter.
  • Parallel instruction set with unique processor addressing modes.
  • Hardware DO and REP loops.
  • Thre.

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Other Datasheets by Freescale Semiconductor (now NXP Semiconductors)

Part Number Description
56F800 16-bit Digital Signal Controllers
56F801 16-bit Digital Signal Controllers
56F8013 16-bit Digital Signal Controllers
56F8014 16-bit Digital Signal Controllers
56F802 16-bit Digital Signal Controllers

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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56F805 Data Sheet Preliminary Technical Data 56F800 16-bit Digital Signal Controllers DSP56F805 Rev. 16 09/2007 freescale.com Version History Rev. 16 Document Revision History Description of Change Added revision history. Added this text to footnote 2 in Table 3-8: “However, the high pulse width does not have to be any particular percent of the low pulse width.” 56F805 General Description • Up to 40 MIPS at 80MHz core frequency • DSP and MCU functionality in a unified, C-efficient architecture • Hardware DO and REP loops • MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes • 31.