56F826 Datasheet | Freescale Semiconductor

56F826 Data Sheet Preliminary Technical Data .. 56F800 16-bit Digital Signal Controllers DSP56F826 Rev. 14 01/2007 freescale. 56F826 General Description - - - - Up to 40 MIPS at 80MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture Hardware DO and REP loops MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes 31.5K × 16-bit words (64KB) Program Flash 512 × 16-bit words (1KB) Program RAM 2K × 16-bit words (4KB) Data Flash 4K × 16-bit words (8KB) Data RAM 2K × 16-bit words (4KB) BootFLASH Up to 64K × 16-bit words each of external memory expansion for Program and Data memory - - - - - - - - One Serial Port Interface (SPI) One additional SPI or two optional Serial munication Interfaces (SCI) One Synchronous Serial Interface (SSI) One General Purpose Quad Timer JTAG/OnCE™ for debugging 100-pin LQFP Package 16 dedicated and 30 shared GPIO Time-of-Day (TOD) Timer - - - - - - EXTBOOT RESET IRQA IRQB 6 JTAG/ OnCE Port TOD Timer Interrupt Controller Program Controller and Hardware Looping Unit Address Generation Unit Data ALU 16 x 16 + 36 → 36-Bit MAC Three 16-bit Input Registers Two 36-bit Accumulators Bit Manipulation Unit VDD 3 VSS 4 4 VDDIO VSSIO 4 Analog Reg VDDA VSSA Low Voltage Supervisor 4 Quad Timer or GPIO Program Memory 32252 x 16 Flash 512 x 16 SRAM Boot Flash 2048 x 16 Flash Data Memory 2048 x 16 Flash 4096 x 16 SRAM PAB PDB XDB2 CGDB XAB1 XAB2 INTERRUPT CONTROLS 16 IPBB CONTROLS 16 16-Bit 56800 Core PLL Clock Gen CLKO XTAL EXTAL 6 SSI or GPIO SCI0 & SCI1 or SPI0 SPI1 or GPIO Dedicated GPIO 4 COP/ Watchdog COP RESET MODULE CONTROLS ADDRESS BUS [8:0] DATA BUS [15:0]...