BSC9131
overview of the feature set:
- High-performance 32-bit e500 core built on Power Architecture® technology:
- 36-bit physical addressing
- Double-precision floating-point support
- 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache
- Enhanced hardware and software debug support
- 800 MHz/1 GHz clock frequency
- 256-Kbyte L2 cache with ECC; also configurable as SRAM and stashing memory
- One SC3850 core subsystem, which connects to the following:
- 32 Kbyte 8-way level 1 data/instruction cache (L1 Dcache/ICache)
- 512 Kbyte 8-way level 2 unified instruction/data cache (L2 cache/M2 memory)
- Memory management unit (MMU)
- Enhanced programmable interrupt controller (EPIC)
- Debug and profiling unit (DPU)
- Two 32-bit quad timers
- Multi...
