MC68HC908AS32A Datasheet | Freescale Semiconductor

Description Reformatted to meet new publications guidelines. Modules updated with additional data September, 2005 1.0 1.4.16 BDLC Receive Pin (BDRx D) - Corrected name of BDLC receive pin to BDRx D. Removed Keyboard Interface Module Removed Timer Interface Module B Removed all references to TIMB and TBCLK Figure 1-3. 64-Pin QFP Assignments (Top View) - Added pin assignment diagram for the 64-pin QFP. May, 2006 Figure 2-2. I/O Data, Status and Control Registers - Corrected two register entries: SPI Status and Control Register (SPSCR) FLASH Control Register (FLCR) Chapter 20 Ordering Information and Mechanical Specifications - Added information pertaining to the 64-pin quad flag pack (QFP). Page Number(s) Throughout 25 N/A N/A 23 32 38 271 MC68HC908AS32A Data Sheet, Rev. 2.0 4 Freescale Semiconductor List of Chapters Chapter 1 General Description - - - - - - - - - . . . 19 Chapter 2 Memory - - - - - - - - - - - . . . 29 Chapter 3 Analog-to-Digital Converter (ADC)- - - - - - - . 59 Chapter 4 Byte Data Link Controller (BDLC) - - - - - - - . 67 Chapter 5 Clock Generator Module (CGM) - - - - - - - . . . 97 Chapter 6 Configuration Register (CONFIG1) - - - - - - . . . . 115 Chapter 7 Configuration Register (CONFIG2) - - - - - - . . . . 117 Chapter 8 puter Operating Properly (COP) -...