MC68HC908QY2
Description
Page Number(s) N/A Initial release N/A 1.2 Features - Added 8-pin dual flat no lead (DFN) packages to features list. MCU Pin Assignments - Figure updated to include DFN packages.
Key Features
- Added 8-pin dual flat no lead (DFN) packages to features list. 19 Figure 1-2. MCU Pin Assignments
- Figure updated to include DFN packages. 21 Figure 2-1. Memory Map
- Clarified illegal address and unimplemented memory. 27 Figure 2-2. Control, Status, and Data Registers
- Corrected bit definitions for Port A Data Register (PTA) and Data Direction Register A (DDRA). 27 Table 13-3. Interrupt Sources
- Clarified oscillator trim option 92 device. Figure 11-5. Oscillator Trim Register (OSCTRIM)
- Diagram updated for clarity. 150 0.1 Figure 12-1. I/O Port Register Summary
- Corrected bit definitions for PTA7, DDRA7, and DDRA6. 99 Figure 12-2. Port A Data Register (PTA)
- Corrected bit definition for PTA7. 100 Figure 12-3. Data Direction Register A (DDRA)
- Corrected bit definitions for DDRA7 and DDRA6. 101 Figure 12-6. Port B Data Register (PTB)
- Corrected bit definition for PTB1 103 Chapter 9 Keyboard Interrupt Module (KBI)
