MC9S08DV96 Overview
MC9S08DZ128 MC9S08DZ96 MC9S08DV128 MC9S08DV96 Data Sheet HCS08 Microcontrollers MC9S08DZ128 Rev.
MC9S08DV96 Key Features
- 40-MHz HCS08 CPU (20-MHz bus)
- HC08 instruction set with added BGND instruction
- Support for up to 32 interrupt/reset sources
- 24-channel, 12-bit resolution, 2.5 μs conversion time, automatic pare function, temperature sensor, internal bandgap ref
- Two analog parators with selectable interrupt on rising, falling, or either edge of parator output; pare option to fixed
- CAN protocol
- Version 2.0 A, B; standard and extended data frames; Support for remote frames; Five receive buffers with FIFO storage s
- Two SCIs supporting LIN 2.0 Protocol and SAE J2602 protocols; Full duplex non-return to zero (NRZ); Master extended brea
- Up to two SPIs; Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; Master or Slave mode; MS
- Up to two IICs; Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; General Cal