MC9S12KL128 Description
of Changes Change load cap value on VDD and VDDPLL. Correct expanded bus timing from 20MHz to 25 MHz. Move ATD interrupt vector from $ffd0 to $ffd2.
MC9S12KL128 Key Features
- 15 Modes of Operation
- 17 MC9S12KG(L)(C)128(64)(32) Block Diagram
- 19 MC9S12KT(G)256 Block Diagram
- 20 Device Memory Map
- 21 Detailed Register Map
- 27 Part ID Assignments
- 53 2.2 Signal Properties Summary