MCF54451 Datasheet | Freescale Semiconductor

Features - Version 4 Cold Fire® Core with MMU and EMAC - Up to 410 Dhrystone 2.1 MIPS @ 266 MHz - 16-KBytes instruction cache and 16-KBytes data cache - 32-KBytes internal SRAM - Support for booting from SPI-patible flash, EEPROM, and FRAM devices - Crossbar switch technology (XBS) for concurrent access to peripherals or RAM from multiple bus masters - 16-channel DMA controller - 16-bit 133-MHz DDR/mobile-DDR/DDR2 controller - USB 2.0 On-the-Go controller with ULPI support - 32-bit PCI controller @ 66MHz - ATA/ATAPI controller - 2 10/100 Ethernet MACs - Coprocessor for acceleration of the DES, 3DES, AES, MD5, and SHA-1 algorithms - Random number generator - Synchronous serial interface (SSI) - 4 periodic interrupt timers (PIT) - 4 32-bit timers with DMA support - DMA-supported serial peripheral interface (DSPI) - 3 UARTs - I2C bus interface This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2008. All rights reserved. Table of Contents MCF5445x Family parison - - - - . . . .4 Ordering Information- - - - - - . . .5 Hardware Design Considerations - - - - . . .5 3.1 Analog Power Filtering - - - - - .5 3.2 Oscillator Power Filtering - - - - . . . .6 3.3 Supply Voltage Sequencing - - - - . .6 3.3.1 Power-Up Sequence - - - - . .7 3.3.2 Power-Down...