Description
Page Number(s) N/A 19 21 28 28 124 113
97
104 160 105 106 107 109 83 49 91 169 187 185 49
0.2
4.2
Features
- Added 8-pin dual flat no lead (DFN) packages to features list. Figure 1-2. MCU Pin Assignments.
- Figure updated to include DFN packages. Figure 2-1. Memory Map.
- Clarified illegal address and unimplemented memory. Figure 2-2. Control, Status, and Data Registers.
- Corrected bit definitions for Port A Data Register (PTA) and Data Direction Register A (DDRA). Table 13-3. Interrupt Sources.
- Corrected vector addresses for keyboard interrupt and ADC conversio.
MCHC908QY4 Datasheet
